SDRAM problem in SOPC builder

Michel, if the SDRAM is not connected to the Nios processor (instructions or data master ports), the SDRAM_BASE will not defined in system.h.

Please have a look to that pdf:

ftp://ftp.altera.com/up/pub/altera_material/9.1/tutorials/verilog/de2-115/using_the_sdram.pdf (ftp://ftp.altera.com/up/pub/altera_material/9.1/tutorials/verilog/de2-115/using_the_sdram.pdf)

There is a tutorial how to use the SDRAM on DE2-115.

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so how do i know the software initialize memory in the SDRAM and not in the processor cache, SRAM, RAM, or somewhere else?

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Memory initialization is done for the address range you give as parameters in the malloc() funtion. Cache is used to speed up execution if code and data access from slow external memory. Just parts of the data are stored temporary in the cache.

If you need uncached access (e.g. if other masters have access to the SDRAM and manipulate data) there are special functions to do that (alt_uncached_malloc() or alt_remap_uncached()), see:

http://www.altera.com/literature/hb/nios2/n2sw_nii52010.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=alt_remap_uncached (http://www.altera.com/literature/hb/nios2/n2sw_nii52010.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=alt_remap_uncached)

By default Nios/e and /s don't use data cache.

regards,

Jens