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Altera_Forum's avatar
Altera_Forum
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20 years ago

SDRAM PLL clock output

Has anyone ever got the following warning regarding the SDRAM PLL clock output:

warning: pll "sys_pll1:sys_pll|altpll:altpll_component|pll" output port clk[2] feeds output pin "sdram_clk" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use pll dedicated clock outputs to ensure jitter performance

My SDRAM clock output signal is assigned to "PLL5_OUT1p"

I thought this meant that I had to go into the assignment editor and assign, for example, PLL5 to the SDRAM clock output signal name. When I try to do that the fitter fails. Does anyone know why I get this, and furthermore how to correct it?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    You should check the pll chapter on the device handbook.

    The input clk and output clk must feed to/from the same pll directly.

    If the input clock does not match the pll, it wont fit.

    If the output clock does not match, it will warn of the jitter.