SDRAM + NIOS not working

OK after further testing I decided to scope the sdram_clk signal against clk_in and found significant jitter. So this might also explain why my memory test makes the nios to hang up after it passes offset + 0x4B - astonishingly that it works until this address.

//#include "sys/alt_stdio.h"# include "altera_avalon_pio_regs.h"
int main()
{ 
 // alt_putstr("Hello from Nios II!\n");
    unsigned char ledstate;
    unsigned int memory_base = 0x02000000;
    int contentcount;
    unsigned int content;
    ledstate = 255;
   while(memory_base < 0x0200004C) { //0x0200004B still works
       contentcount = 0;
        while(contentcount < 16) {
                content = 0;
                content += (1<<contentcount);
                IOWR_16DIRECT(memory_base, 0, content);
                if(IORD_16DIRECT(memory_base,0) == content) ledstate &=~ (1<<4);
                    else {
                            ledstate  &=~ (1<<6);
                        }
                        contentcount++;
if(memory_base & 0x02000049)  ledstate &=~ (1<<7);
           else  ledstate |= (1<<7);
if(memory_base & 0x0200004A)  ledstate &=~ (1<<5);
           else  ledstate |= (1<<5);
IOWR_ALTERA_AVALON_PIO_DATA(0, ledstate);
        }
memory_base++;
   }
ledstate = 255;
 IOWR_ALTERA_AVALON_PIO_DATA(0, ledstate); // just to see whether NIOS hangs up or not
while(1);
 return 0;
}

Further investigating revealed that only dedicated pins shall be used as a PLL clock output. The board containing the FPGA I recently purchased on ebay seems to be not connecting sdram_clk with the pin 43 (PLL1) or the pin 113 (PLL2) – accordingly to the datasheet these are the only PLL’s of the EP4CE6xxxx devices.

If I just use one megawizard- generated pll the fitter will auto assign it with pll1 having its output @ pin 43. On my demoboard the SDRAM_clkin goes to PIN 60 of the FPGA which is not an PLL designated output. I will probably rewire the pcb by changing the tracks connected to 43 and 60 to see if my hypothesis is correct.