SDRAM + NIOS not working

Dear Forum

after further investigating my problem to connect the FPGA and SDRAM I again checked whether writing and reading works on all addresses – unfortunately I made a mistake in my first trial. Now after correcting this mistake it turned out that writing and reading just works for a few addresses – no matter which phase shift I've selected for the PLL (- which is quite strange). This is the nios code I’ve used to check access:

unsigned char ledstate = 255;
unsigned int memory_base = 0x02000000; //sdram baseaddress
 
while (memory_base < 0x02000053) { //5a 
        ledstate = 255;
     IOWR_16DIRECT(memory_base, 0, 0x50A0);
      if(IORD_16DIRECT(memory_base,0) == 0x50A0) ledstate &=~ (1<<4);
      else {
         ledstate  &=~ (1<<6);
      }
      memory_base+=2;
      IOWR_ALTERA_AVALON_PIO_DATA(0, ledstate);
}

I've got the following result:

0x53 addresses can be accessed for the QSYS sdram_controller setting: 11 rows and 8 columns

0x5A addresses can be accessed for the QSYS sdram_controller setting: 13 rows and 9 columns

I think that my sdram-controller has the wrong setting. From the datasheet of the used SDRAM (W9864G6KH) I got this information: 1048576 words x 4 banks x 16 bits. Unfortunately there is no (I didn't found any) information on the number of rows and columns.

I would be very happy if someone could give a hint how to get the correct sdram-controller configuration.