S10 SoC does not show up in lspci

Hi!

I think you must use CvP configuration. I use it on my Achille development kit.

You must enable CvP mode for your design to compile it. It creates à partial design (with the PCIe interface) that you download on the board prom, and an another file (core.rbf) that you must download after with the PCIe interface (with the appropriate driver of course).

So it leads to that following step:

At power up, partial design is load before mother board scan the PCIe bus, so the card will be detected.

PCie Driver on the mother board download the rest of the design in the fpga

Reboot (without switching off S10 SOC of course) must be perform on the host to "refresh" the PCIe scan.

Or more simple download all your design (PCIe interface and User design) in the prom without CvP mode.

Switch on the system

Reboot (once again without cutting off S10 power) host and your PCIe interface must be present.

Regards