--- Quote Start ---
PeFarina,
It is a common practice to share address and data pins between SRAM and Flash memory to reduce the number of pins required in your FPGA design. If this is your case, you need to add a pin-sharer module in SOPC Builder. I'm more familiar with Qsys, but I imagine the configuration is similar. I attached a screen shot of my Qsys design to show how the pin sharer connects the SRAM and Flash. If you have separate address and data pins for your SRAM, then you don't need the pin sharer.
--- Quote End ---
thanks,
i have separate address and data pins for my SRAM, i´ve checked on pin planner.
if i do a memory test as you have explained me( Tcl Console) does it mean that the sram component(terasic_sram) is working? or the access to memory is done by other way.
how can i see the value of vector reset?because i can move its address but i don know if when i change the files(.bss .heap .rodata .rwdata .stack .text) to sram the reset vector changes too.
if you want more info about my project i will send you.
i've attached the eclipse console
Honored Contributor
