Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Running program in SDRAM

Dear all,

I just solided on FPGA board with Cyclone and SDRAM.

I tried the example Hello_World_Small program in on_chip_ram, and received the output via UART.

Then I add the SDRAM Controller (with the parameters described in SDRAM datasheet) and connect the corresponding signal to SDRAM Chip, recompile the system, set the rest point to SDRAM in SOPC Builder. Also in the NIOS IDE, I set the Program running in SDRAM.

What I got is:

Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00

Pausing target processor: OK

Downloading 00800000 ( 0%)

Downloaded 6KB in 0.1s

Verifying 00800000 ( 0%)

Verify failed

Leaving target processor paused

00800000 is my SDRAM Address.

What may cause such problem?

Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    redsun,

    > What may cause such problem?

    There are many potential causes. Here are some:

    - SDRAM was not placed correctly (shorts/opens on pads).

    - Bad traces between Cyclone and SDRAM.

    - SDRAM clock doesn't meet timing requirements.

    - Pins are not assigned correctly.

    - SDRAM timing parameters are incorrect.

    - SDRAM is not actually mapped to 0080_0000.

    Check the easy stuff first (pin assignment, timing parms, base addrs) first. The check

    your timing analyzer results against your board layout -- you may need to shift your

    SDRAM clock phase.

    Finally, break out a scope and add an SDRAM memory test to your hello_world that runs

    out of on chip ram Make sure you bypass/don't implement the data cache.

    Regards,

    --Scott