The Byteblaster-II is designed and laid out very differently to Byteblaster/Byteblaster-MV (which were based around a 74244).
I've ended up slugging all of the JTAG signals (each with 33pF); I suspect that crosstalk from the TDI/TMS signals is occuring when the TCK signal goes low thus causing false clocking (which could be complete ballerks but it's the best reasoning I can conjure - I have experienced double-triggering on Cyclones that I didn't get on MAX devices before).
I've also widened the SRAM timings (ridiculously long for now - like 50/100ns)
Also make sure there are no other devices on the bus fighting the SRAM when the JTAG debug module is trying to program it.
One thing I did notice is that a 32-bit word write on a 16-bit device is done with 2 write pulses, but with chip select asserted throughout, with the A1 change between the write pulses. The reads are done with separate chip selects. I'm pretty sure most memory devices can handle being operated in this way.