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Are you saying that the NIOS II in the simulation is the actual RTL model and it is the actual design?
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You can simulate a NIOS II processor;
http://www.altera.com/support/examples/nios2/exm-simulating-niosii.html For your understanding of how the NIOS II processor boots, I would create a new design that does not include complications like PCIe, but has the processor and its boot memory, and some external I/O, one of which is a reset signal that you can toggle in your testbench. By watching the NIOS II processor buses, you will see what happens at reset. You can then change the NIOS II processor configuration and see how that affects the reset sequence. Chances are you will have an "ah-ha!" moment, and then see what you need to do for your hardware.
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I have made some progress based on the NIOS II reset discussion. I committed both the FPGA configuration and the NIOS software to FLASH and , powered on and the alive LED from the FPGA is flassing and the NIOS alive LED is on solid, due to PIO latch reset.
When I go to the Eclipse Run Configurations -> Target Connection -> Debug section I can deselect the Download Software button, Deselect the Reset System button and Select the Start NIOS button and the NIOS PIO led starts to flash ... I believe this is a fair indication that all I need to do is to move the NIOS Reset from the JTAG debug reset to the regulat reset or possibly have QSYS simply OR in the regular reset that goes to the other cores.
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That sounds reasonable. Try it and see :)
Cheers,
Dave
Honored Contributor
