Honored Contributor
Honored ContributorOk Dave ... so you provided an Avalon MM Master and Avalon MM Slave Modelsim testbench which was very useful.
Are you saying that the NIOS II in the simulation is the actual RTL model and it is the actual design ? I was thinking the NIOS II was a BFM with a Avalon MM Master for Instructions and Data ... If it is the actual design, then after reset is deasserted it will fetch the reset vector. That would be great. I would be very interested in a pointer or from memory, you indicated to get the system to generate a testbench and then start with that as a modification point. I would also need to initialize the FLASH memory with the actual binary code that results from programming FLASH with the *_sw.flash file . I have made some progress based on the NIOS II reset discussion. I committed both the FPGA configuration and the NIOS software to FLASH and , powered on and the alive LED from the FPGA is flassing and the NIOS alive LED is on solid, due to PIO latch reset. When I go to the Eclipse Run Configurations -> Target Connection -> Debug section I can deselect the Download Software button, Deselect the Reset System button and Select the Start NIOS button and the NIOS PIO led starts to flash ... I believe this is a fair indication that all I need to do is to move the NIOS Reset from the JTAG debug reset to the regulat reset or possibly have QSYS simply OR in the regular reset that goes to the other cores. Thanks alot, Bob.
