--- Quote Start ---
I believe you are saying the NIOS core can be released from reset or controlled via a register output to start executing the reset vector and the system ( rc ) side could do the load and reset register operation.
--- Quote End ---
The NIOS II processor is "just logic". If you hold that logic in reset, it'll do nothing until you enable it. This means that you can manipulate the memory map via PCIe, and then release the processor from reset.
I have not done this with the NIOS II processor, but I have several hundred boards with DSPs on that I use this technique with, since I can then guarantee that they are all booted with exactly the same image (served from a common NFS filesystem).
Cheers,
Dave
Honored Contributor
