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Thanks! :)
I haven't tried a class code of 0, so hadn't had that one trip me yet :)
In what way?
The tests I did in this thread (see the PDF)
http://www.alteraforum.com/forum/showthread.php?t=35678 have pre-fetchable regions.
Why IOCTL codes? You can use the mailboxes and interrupts to create an inter-locked handshake. Here's an old PCI example ...
http://www.ovro.caltech.edu/~dwh/correlator/pdf/cobra_driver.pdf Why do you need this? If you are DMAing data, then use an interrupt to indicate the end of the transfer.
Here's what I would do (assuming you have SDRAM on the board for the NIOS II processor);
1. Instantiate a NIOS II core that boots from SDRAM.
This core powers-on with its reset asserted. The reset register would be something the host can toggle, eg., an Avalon-MM register.
2. Use the host to copy the NIOS II images into SDRAM.
3. Use the host to release (deassert) the reset line.
The NIOS II processor would then boot. The host can wait for a message from the NIOS II in the mailbox.
Here I assume that you have a "mailbox" for the host-to-device and another for device-to-host transfers, and that these two mailboxes generate interrupts at their respective device.
Cheers,
Dave
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Hi Dave, been working on this for almost a year now on and off.
I am interested in your statement that the NIOS II core powers-on with reset asserted ... possibly that is the reason the NIOS II doesn't start up automatically when I commit both the FPGA configuration to FLASH and the NIOS II software to FLASH . I can't see any mention in the examples of having to explicitly release the NIOS II reset ( or to generate a reset "interrupt " to force execution at the reset vector ... Can you point me to anything there as I believe I am close to running the FPGA + NIOS II out of FLASH.
Anyhow ... I had an idea on the NIOS II software load via the host. Can you comment on this.
1. Since the Altera cards all have FLASH, start the NIOS II out of flash executing boot loader code .
2. Modify the boot loader expect the code to be found at SSRAM location x.
3. Modify the boot loader to poll a doorbell register set by the host via some register mapped to a BAR.
4. Have the host load the code at SSRAM loaction x .
5. Have host set the doorbell indicating to the boot loader to go and load code in SSRAM and begin execution of user code.
The alternative would be to have the FLASH accessed via a BAR register and when the user SW FLASH is to be updated, have the
host update the user FLASH code and then restart the NIOS II core ... that may be more straight forward.
Regards, Bob.
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