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Awesome!
If you look in the Qsys memory map (use the memory map tab), it will show you the addresses for each Avalon-MM master. The BAR registers are a PCIe slave, but an Avalon-MM master. If you have a BAR that maps to a 4K block of Avalon-MM registers, then the PCIe 64-byte address should map to an Avalon-MM master address, and then that will map to your slave (with address LSBs dropped depending on whether its an 8-bit, 16-bit, or 32-bit slave).
Huh? The CRA registers are for your Avalon-MM masters to use, I don't think it was intended for you to loop back onto a BAR register for PCIe access.
Sorry, I'm not sure what the IMEM you are referring to is.
Modelsim simulation of the system would help resolve addressing issues like this.
Cheers,
Dave
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Dave the example device I have sets the Cra translation table entries up via a BAR register at the end of the DD probe code .. just before the endpoint is enabled.
The NIOS system I have only has IMEM ... I have IMEM at 0x00010000 - 0x0001ffff and CRA at 0x00020000 - 0x00023fff somehow when I trie to set the CRA tables at 0x00021000 the table entry gets written to IMEM at 0x00011000 .. I think this may be due to the BAR1 offset I am giving which is the absolute offset
and not a relative offset . Thanks Bob.
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