Honored Contributor
Honored ContributorHi Bob,
--- Quote Start --- on re-reading your suggestion to load the NIOS code via the PCIe link ... I now understand you are saying to load up the SRAM data and the SRAM controller will be in reset ... upon releasing that reset the NIOS core will start ... does that mean that the NIOS core will be stalled with a fetch to the reset vector memory location, until the SRAM controller is active and can honor the first Avalon MM bus read request ? --- Quote End --- If you assert the NIOS II processor reset pin, it will sit there doing absolutely nothing. If the NIOS II processor is supposed to boot from SRAM or an external SDRAM, then it will not boot until reset is released. I use a "similar" scheme for booting a DSP. The DSP external bus routes through an FPGA. The "memory map" of that FPGA normally locates flash at the DSP reset location, however, by changing an FPGA register, I can remap SDRAM over the flash locations. This allows me to copy DSP boot code into SDRAM, reset the DSP, flip the DSP address decoding bit, and then release the DSP reset, and viola, it boots from SDRAM (none the wiser). This allows the flash to contain a basic image, whereas my run-time code gets delivered from a version controlled file-system. I never have to wonder which version of code is running on the DSP, as I know for certain it is the latest code. Cheers, Dave
