Resource Collisions when installing PCIe DD

Dave Thanks for the reply.

"have pre-fetchable regions."

I believe pre-fetchable space is generally supported but I believe the particular Linux I am working with which is a development version may not support pre-fetchable memory on the endpoint somewhere down in the kernel resource related code ... I can investigate this but not right now.

"Why IOCTL codes? You can use the mailboxes and interrupts to create an inter-locked handshake. Here's an old PCI example ..."

I am just using IOCTL at this tome to provide some simple system side facility to test code running at the application level.

"Why do you need this? If you are DMAing data, then use an interrupt to indicate the end of the transfer."

I can understand why this may not be obvious ... the short answer is that I am taking a verification test suite which includes a "produce consumer" stress test and

supporting it in an Emulation and Post-Silicon environment . The produce / consumer test could use an interrupt to signal that the transfer is complete but the implement producer / consumer

test transfers data , and has a flag and status value to synchronize between the producer and consumer. The flag and status can randomly mapped to endpoint memory or system memory in all possible permutations. So the ARM processor in the system produces data and the NIOS core consumes data. The reason for this is to stress bridges between the producer and consumer which need to obey PCI ordering rules.

So ... this isn't a simple DMA data transfer but a stress test to run verification tests in a post-silicon validation environment.

In general MSI interrupts will stay in order across bridges since the MSI is just another write and will stay ordered behind the write data. In the producer / consumer test the write data may target endpoint memory while the endpoint NIOS polls the flag in system memory to determine the data write has completed. If the bridges honor PCI ordering rules , the flag read completion will flush posted data writes in bridges. I am stressing that activity in this test. I hope that makes sense as a "normal" data transfer may involve DMA followed by an interrupt but we can't constrain all activity to be "normal".

Best Regards, Bob