Honored Contributor
Honored ContributorHi Dave and team, I owe you an answer here ... I wasn't really getting anywhere adding printk messages to the PCIe kernel code so elected a different approach.
I tried a $30 dual USB PCIe endpoint from Fry's and it had resources allocated just fine. I recorded the dmesg output to a text file then did the same with the Arria V starter kit board with my Gen1 X1 PCie design and again recorded the dmesg output to a text file. I then diffed the two outputs and evaluated the differences. Oh, I should say that I modified the FPAG design to match the BAR's and sizes that were showing up on the dyal USB endpoint ... it still failed with a "resource conflict" Anyhow the first difference was the Class code returned from the endpoint config space. The FPGA was returning 0x00000000, since I was not setting it to anything and the USB PCIe endpoint card returned a non-zero value indicating some serial bus endpoint. So ... I copied that class code to the FPGA design and the resources were allocated as expected. I have not traced through the PCIe kernel code to determine why a Class of 0x00000000 causes problems but the PCIe reference indicates a value of 0x00000000 indicates some early adapter so I assume the kernel code is not supporting a 0x00000000 code. I have made progress on the Linux device driver based on the 2 samples provided from Altera. I also found that the Linux I have doesn't support pre-fetchable memory attribute on the BARS. And I set the BAR0 to 32 bit address space and defined the BAR1 as 32 bit address to access the DMA controller and mail boxes for NIOS <-> ARM system ( rc ) communications . I now have IOCTL functions supporting the ARM system as a "producer" and have NIOS code to implement the "consumer" side ... I plan to add dedicated PCI order checking state machines at the output of the hard PCIe IP at the Avaon MM BAR0 output and where read completion data is mastered ... to monitor dedicated "data" coming down the BAR0 master and a dedicated "flag" pattern which will be a NIOS read completion. As a debug tool I plan to have the order tracking state machine inputs ( patterns) drive FPGA outputs to drive user LED's and be tracked by logic analyzer. Dave, on a new subject, I want to run CVP to manage the FPGA configuration from the system side ... but I also want to load the NIOS .elf or .flash code from the system side as well. Where should I go for advice on say configuring the NIOS Flash from the system side .... I believe maintaining both from the system side is the only reasonable way to manage "configuration" and "code" levels since as a manual operation it would be difficult to manage. Would it be as easy as adding a FLASH controller and having the system update the FLASH diirectly wiith a new .flash file ? Thanks, Bob.
