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Hi , I am facing the same problem . I am new user to Nios , so can anyone please explain how to solve this issue ?
I have a Qsys system with Nios CPU , ON-chip ram and few PIOs . I initialize the on-chip RAM with a .hex file and create the .pof file.
Once I burn the .pof inside the FPGA, on-chip RAM gets initialized and the Nios starts running as expected.
But when the device is running , if I give a manual reset to the Qsys system with an external switch , the processor goes into a reset state and
it stays in reset state even after i de-assert the reset switch.
Also, when a power on reset sequence occurs, the processor will execute code correctly. It only mis-behaves when the reset occurs from an external switch input.
Both the reset vector and exception vector of the Nios Processor is in the On-Chip RAM
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Have you implemented a debounce logic/circuit for the switch?
Have you managed the
cpu_resetrequest and
cpu_resettaken IO available in the nios_cpu component?
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