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NZami's avatar
NZami
Icon for New Contributor rankNew Contributor
7 years ago

remote update IP with cyclone10 LP

Hi, I used the remote update core to load 2 images (factory and application) with cyclone III work with Active parallel mode. Now I try to load the 2 images to cyclone10 LP. I work now at Active Ser...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi NZami,

What is the reconfiguration trigger condition value that you have read back during factory image? Since the FPGA gets revert back into the factory image then you should be able to read back the reconfiguration trigger condition value. You need to set the param[] = 111, read_source[]=01 and trigger the read_param signal. Then when the busy signal is low monitor the data_out[] for the reconfiguration trigger condition value. You can use Signal Tap to monitor these signals.

How did you write the .rpf file into the flash device? The default generated .rpd file from Quartus tools is little endian format. By default the programming the .jic/pof file, the Quartus programmer will perform the bit swapping (LSb first) before writing the data into the EPCS/EPCQ/EPCQA device. Thus you need to perform the bit swapping when using the little endian .rpd file before writing the data into EPCS/EPCQ/ECPQA device. If you set the big endian option in the Convert Programming tools when generation the .rpd file, then you don’t require to perform the bit swapping since the generated .rpd file is in big endian format.

Regards,

Nooraini