regarding the downloading the design in Flash

Are you using a Nios development board by any chance? If so make sure that under the Quartus II device options that "Unused I/O" is not set to ground (that would cause the board to re-config after programming if the reconfig_n signal isn't hooked up).

Also are you sure you want to be using these settings?

"program memory flash

read only memory flash"

That's not going to get you very good performance since the Nios instruction and data masters must access the program/read only data sections.

Hi,

Actually i have set that all the unused pins be assigned as input tri-stated

so i don't think the eproblem u said may arise.

also will there be any problem if i say

that i want to have the program memory in flash and rom memory in flash.

anyway i have set the r/w memory in sdram.

but nothing is working.no response from the system at all after downloading

both sof and the application in flash using the flash programmer.

any more suggestions???

thanks in advance

prasad

Hi prasad,

What board are you using?

> in my application code i have written only printf statements

Are you using the hal or are you using custom code?

> but nothing is working upon reset or reset configuration

What does this mean? The FPGA does not complete configuration? Your initialization code does not

run? You don't see the output of your printf statements?

Are you using a serial port/uart or the jtag uart?

> any more suggestions???

Use nios2-console. Reset the cpu, check your startup code at the reset address, test your memory,

and try single stepping, set a hardware breakpoint at main(), etc. Then let us know what you

observe.

Regards,

--Scott

Hi Scott,

Thanks for the response.

actually i am using the nios development kit

also i am using HAL libraries only.

i am able to downlaod the design(application + sof)

through the flash programmer .

but when i reset the processor no response.

i am using the jtag uart(usb) as my std err and std output.

when i reset the configuration, corrresponding configuration led is glowing

and configuring the fpga.

but no response.

also in the earlier replies i have given my reset address and other setting of the system library.

please suggest to me how to rectify the problem.

i have set 2 conditions

in sopc

1) reset address in flash offset 0x00000000 and address 0x01000000

2) exception address in flash offest 0x00000020 and address 0x01000020

in nios system library properties

a) http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif c)

program memory -- flash program memory -- sdram program memory -- sram

rom memory -- flash rom memory -- sdram rom memory -- sram

r/w memory -- sdram r/w memory -- sram r/w memory -- sram

for any of the combinations above it is not working i.e. no response if i reset the processor

but dowloading in flash and configuring the fpga from flash when reseted is happening

also i want to confirm is pll mandatory for the above conditions? ie. for sdram and sram?

i did not use pll in the design.

but atleast soem things should come right?

anyway suggest me on this

thanks

prasad

Hi prasad,

> when i reset the configuration, corrresponding configuration led is glowing

> and configuring the fpga.

> but no response.

...

> please suggest to me how to rectify the problem.

I did ... in my last post. Did you try any of those suggestions?

Regardless, when the sum total of your observations is "no response" ... it&#39;s time to keep

things simple and take smaller steps. Forget about programming flash and starting your app

at power-on. Get it working first ... then worry about the fancy stuff later:

1. Change your exception address to sdram.

2. Re-build your system.

3. Load your design via jtag (using Quartus Programmer for example).

4. Change your system library properties to put everything in SRAM.

5. Rebuild your application.

6. Start debugging -- by downloading your app to SRAM.

If you still get "no response" it&#39;s probably time to look at your logic design.

> also i want to confirm is pll mandatory for the above conditions? ie. for sdram and sram?

> i did not use pll in the design.

> but atleast soem things should come right?

/o Before you do anything else ... do yourself a favor and review the example designs

for your particular development kit ... then add the pll to your design.

Regards,

--Scott

Sorry, my bad:

- 1. Change your exception address to sdram.

- 1. Change your exception address to SRAM.

--Scott

Hi,

one more thing i want to clarify

can&#39;t i have my exception address in flash?

what will be the implications?

regards

prasad

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

Hi prasad,

> can&#39;t i have my exception address in flash?

Yes, of course.

> what will be the implications?

You will not be able to change code at the exception address -- which may be just fine for

your application. There are some situations where you may need to change/overwrite the

code at the exception address however ... using u-boot to load the linux kernel for example.

But this all depends on your requirements.

Regards,

--Scott

Hi Scott

actually how much of memory will be consumed for

boot code in flash that will be added by nios IDE in front of the application code.

i think it is just 0x20 bytes. am i wrong

thanks and bye

prasad