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originally posted by prasad_forums@Oct 5 2005, 10:14 PM
but it should put only reset vector and exception vector at reset address and exception addresses no? --- Quote End ---
I see your confusion. You're thinking of other CPU architectures, where the CPU loads an address from a reset vector on startup into the PC and starts execution from there.
Nios2 doesn't do that. That reset address you put in SOPC builder is where it starts execution. No vector fetching. Nios2 doesn't even have a vector table; all exceptions result in the CPU state being saved and the processor jumping to the exception address.
So say you run entirely from flash at address 0x0. 0x0 through 0x1F contain a small bit of code that clears the instruction cache and jumps to _start. Address 0x20 is the start of the exception handler routine. _start is usally located somewhere after the exception handler routine.
Now say you boot from flash at 0x0 but run from SDRAM at 0x10000000. The flash contains a small bootloader which copies one or more data blocks from flash to SDRAM, then jumps to the _start address in SDRAM, and uses no RAM, just registers. The data to be copied to the SDRAM resides in the flash, immediately after this bootloader, and is followed by the SDRAM address of the _start routine. The SDRAM, after the bootloader is done, will contain the exception handler at 0x10000020, followed by the _start routine, followed by the rest of your code, then .rodata, then .rwdata, then .bss. SDRAM addresses 0x10000000 to 0x1000001F are unused.
How does it know which to do? It looks at whether or not your exception handler address is in volatile memory (e.g. SDRAM) or not (e.g. flash).
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