Reference example for NIOS writing to HPS's DDR3 on CycloneV SoC ?
Hi, I am looking for a reference example, ideally for the DE0-Nano SoC (but any CycloneV SoC based example will do), that would allow me to test the following configuration: a NIOS2 implemented in ...
Yes, I am using NIOS as a master. I figured out a few things:
first, that since I want to access both the HPS memory through the bridge, AND internal devices in the FPGA, I need to add an Address Span Expander, otherwise the whole 32 bit address space of the NIOS is mapped to the 32 bit space of the HPS memory, and there is no address left to access FPGA peripherals.
So I added such an Address Span Expander, and I am mapping 16MB of the HPS memory, at HPS offset 0x32000000
But there is something I do not understand in Qsys behavior:
when I initially connect the "expander master" port of the expander to the f2h bridge, everything seems to be fine:
but if I do "Assign Base Addresses", then I get an error about NIOS not supporting address space above 32 bits: and I just noticed that this is because the addresses of all other peripherals have been recomputed and are now above 0xffffffff
Why does adding the expander and recomputing base addresses result in the remapped address being over the 32 bit address range ?
I am still interested in a simple reference example corresponding to this scenario, anyway.
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