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Altera_Forum
Honored Contributor
19 years ago<div class='quotetop'>QUOTE </div>
--- Quote Start --- I'm becoming very suspicious that our processor configuration isn't right. The CPU reset address is in SDRAM, so that's where the .entry section is ending up. Your ROM configuration shows the .entry section in flash along with .text, .rodata, etc.[/b] --- Quote End --- Probably makes sense - the Altera example design has a reset address at offset 0x0 in flash and an exception address at offset 0x20 in sdram.