Read/Write from SDRAM without Avalon

The NIOS processor is not required. If you use the SOPC builder you can basically hook up any device to the FPGA. Example: you can hook up an 8051, via the avalon bus that uses SDRAM.

Using SDRAM without the confort of the SOPC is another ball game. You can integrate various SDRAM IPs and hook up your own devices, but you will have to put some more effort in. One site, I think, is www.cmosexod.com. I think there is an SDRAM IP core that allows you to drive it like SRAM.

In the end the SDRAM controller looks like SRAM device. You need to generate an address, write ot read data and pulse read and write signals. The only problem I see is when your speed gets too high and the SDRAM controller skips a clock (wait state) or 2.

Victor Schutte

http://www.zerksus.com (http://www.zerksus.com)

Thanks for your answer Victor, much appreciated.

In case I am generating the design through SOPC, it means I will have to use Avalon. However, would it be possible to access SDRAM without the mean of Avalon?

Thank you in advance,

John.

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originally posted by victors@Jan 14 2006, 10:34 AM

the nios processor is not required. if you use the sopc builder you can basically hook up any device to the fpga. example: you can hook up an 8051, via the avalon bus that uses sdram.

using sdram without the confort of the sopc is another ball game. you can integrate various sdram ips and hook up your own devices, but you will have to put some more effort in. one site, i think, is www.cmosexod.com. i think there is an sdram ip core that allows you to drive it like sram.

in the end the sdram controller looks like sram device. you need to generate an address, write ot read data and pulse read and write signals. the only problem i see is when your speed gets too high and the sdram controller skips a clock (wait state) or 2.

victor schutte

http://www.zerksus.com (http://www.zerksus.com)

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John

Yes, you should be able to do it without the Avalon bus, but then you have to generate all the bus signals to the SDRAM core.

A more hands-on approach would be to use Jeung Joon Lee&#39;s SDRAM IP at http://www.cmosexod.com (http://www.cmosexod.com) or maybe even the DDR design from http://www.opencores.org/projects.cgi/web/ddr_sdr/overview (http://www.opencores.org/projects.cgi/web/ddr_sdr/overview)

SDRAM is one of those dodgy devices. Rather stick to a design someone else spent a few weeks with before you try your own.

Victor Schutte

http://www.zerksus.com (http://www.zerksus.com)