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Altera_Forum
Honored Contributor
Honored ContributorRead access through Avalon-MM tristate bridge
Hi there, I was simulating an external memory access through Avalon-MM tristate bridge and the data width of my external memory is 16 bits. Everything worked fine except that, it always perform...
Altera_ForumHonored Contributor
Honored ContributorAs well as behaviour of the bus width adapter (which might do cycles with no asserted byte enables), the nios2 processor always asserts all 4 byte enables for its memory reads - regardless of the requested width.
