MCP2515 CANbus implementation in NIOS using alt_avalon_spi_command on 10M50DA

Hi Nitin123,

Currently, the read operation is failing every time after entering configuration mode and also in normal mode.
When I try to verify what I have written, it is not matching — even the timing registers CNF1, CNF2, and CNF3 are reading back as 0xFF.

Answer:
When you mentioned “not matching”, is it all 0xFF? Or there are other values?

• If all read attempts returns 0xFF, it is possible the MCP2515 is not powered on.
• If some read attempts returns valid value, then the MCP2515 is powered on.

The SPI SO line is High-Impedance (aka logic “1”). So, it is likely that the no Data Out is detected on the SO line.

Could you kindly verify if my write and read operations are correct?

Answer:

The write_reg is correct.

As for read_reg, I would imagine the following SPI transaction with your read_reg, which is different from the MCP2515 recommended waveform.

I would suggest this instead:

static uint8_t read_reg(uint8_t addr) {

uint8_t tx_buf[2] = {MCP_READ, addr};

uint8_t rx_buf = 0;

alt_avalon_spi_command(SPI_BASE, SPI_SLAVE, 2, tx_buf, 1, &rx_buf, 0);

return rx_buf;

}

Quick tips :
Using the logic analyser, you can double-check the read_reg() and tinker around its argument until you get the exact same SPI transaction from MCP2515.

1. Manual Chip Select Control

Could you please clarify why this behavior is happening?

The CS toggling is an expected behaviour.

You can replicate this behaviour by giving the flags argument - ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N to alt_avalon_spi_command().

Quick tips :

If you are writing custom SPI driver, perhaps you can take reference from the alt_avalon_spi_command().

For example, about how to not toggle CS:

1. Utilizing HPS CAN Controller Without DDR

As a general procedure, I would suggest taking a known good working Uboot implementation that contains CAN, and strip it down to just only the CAN portion. i.e. take out everything including any DDR setup. It might fit within the HPS OCRAM.