Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Random Resets

I have a design built into a Cyclone III running uClinux on a NIOS II at 100 MHz. I am seeing random resets (linux reboot). They may be tied to accessing a pio in SOPC, but I do not have enough data to tie together the two. If left untouched, the system will run for hours with no issues. Build a new Zimage and it might reset every few minutes. So far I am clueless to the cause. Any help / suggestions would be appreciated.

The fpga is running a video pipeline. Sometimes that pipeline stops, usually it continues to operate. Ocassionally it appears as if a reset occured and the Zimage failed to load.

Power on reset is not connected to the system, instead we generate a reset off the PLLs lock signal. This was looked at with a scope and does not appear to be causing the issue.

linux version 2.6.30

Quartus II 9.1

Cyclone III EP3C55U484I7N

EPCS64N

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    First thing to check with odd behavior like this is that you are meeting timing requirements on the FPGA build. In particular with the memory controller.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    We appear to be ok on timing. I am working with a designer that is very experienced with this type of design.

    We are using Altera's DDR interface to run mobile ddr - not quite correct, but workable. We have a Microtronix and are thinking of changing to that IP.

    Another data point. If I write to a non-existent address and purposely crash the application code, the video pipeline never fails.