RAM -> DMA -> UART, How to set up?

I am close to believing there is a real problem here.

Altera documentation "Embedded Peripherals IP User Guide" (UG-01085 2015.12.16) states:-

DMA

"The DMA controller transfers data as efficiently as possible, reading and writing data at the maximum

pace allowed by the source or destination. The DMA controller is capable of performing Avalon transfers

with flow control, enabling it to automatically transfer data to or from a slow peripheral with flow control

(for example, UART), at the maximum pace allowed by the peripheral."

UART

The Avalon-MM slave port is capable of transfers with flow control. The UART core can be used in

conjunction with a direct memory access (DMA) peripheral with Avalon-MM flow control to automate

continuous data transfers between, for example, the UART core and memory.

The signal to stall the Avalon Master from the Slave is "waitrequest". The UART outputs "readyfordata". These signals are not connected by QSYS!

Connecting them in the QSYS generate code (with inversion) makes DMA->UART partly work. But it skips bytes. Perhaps "readyfordata" does not work as "waitrequest_n" should.

Any thoughts?

I am thinking the documentation might be wrong ? . . .