Forum Discussion
Altera_Forum
Honored Contributor
9 years agoIf the device (SX vs ST) have the same logic density, then their IDCODE will be the same:
https://documentation.altera.com/#/00005773-AA$NT00080225 Now if the density is different, when you use FPGA manager to program the FPGA image, you can code in such a way that the FPGA manager returns error to the program if the attempt to program the FPGA is unsuccessful (which is the case when you program a part with mismatch image). Presumably then you can load the second image which is correct for the aforementioned device. I know this is not pretty... but could be something :)