Quartus question

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originally posted by hootsmon@Apr 20 2006, 10:15 PM

quartus ii gives this warning message:

    warning: found 159 output pins without output pin load capacitance assignment
    warning: pin "enet_ads_n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pf for timing analysis
 ....

q1) does this cause any problems?

q2) any idea what quartus ii settings can be used to fix this?

thanks in advance

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Output pin load capacitance assignment will effect timing simulation results. Based on my understanding, as long as you are not dealing with timing stringent design or board level design no necessary concern is needed.

For basic timing stringent design with small amount of pins, Quaruts II will automatically assign pins which are in similar logic level to the same I/O bank or adjacent I/O banks. Major timing issues can be studied without concerning capacitance.