Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorQsys dual-clock FIFO reset error
I am trying to add a dual-clock on-chip FIFO memory to my system in Qsys. I am exporting the input data, clock, and reset so that I can tie it into my custom logic. I can get a single-clock design ...
Altera_ForumHonored Contributor
Honored ContributorOnce I selected "Create status interface for output" as an option when configuring the FIFO, the build error went away.
