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Altera_Forum
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7 years ago

Qsys Avalon MM Slave needs a slower clock. Best way to do this?

I’m modifying an existing Cyclone V Qsys design which is clocked from the HPS H2F user clock at 100 MHz . I need to add an Avalon Bus slave core to this system which requires a 50 MHz interface. It a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

QSys will automatically take care of synchronizing if the master and the slave are not connected to the same clock. If you need better performance, you can add an Avalon MM clock crossing bridge between the master and the slave.

For the reset signal, it depends on how it is defined on the component. If it expects a synchronous released reset then you need to synchronize it with the 50 MHz clock first, for example with a reset bridge IP.