Q16.0 QSYS SPI(3 Wire Serial) Slave mode has a issue or not-well considered design

My SPISPI(3 Wire Serial) slave mode is configured to be 8 bits width.

The problem is in slave mode, the ipcore only loads rxdata when the whole transmission is done.

If there is a 4 byte phase, only the last byte will be saved into rxdata.

http://www.alteraforum.com/forum/attachment.php?attachmentid=12497&stc=1

I have checked the source code in core_spi_0.v

The RRDY & rx_holding_reg only get updated once for all when SS_n rising up.

  assign forced_shift = ds2_SS_n & ~ds3_SS_n;
          if (forced_shift)
            begin
              if (RRDY)
                  ROE <= 1;
              else 
                rx_holding_reg <= shift_reg;
              RRDY <= 1;
            end

This is another funny thing, the state code was laying there but be used by nowhere, I think this "state == 8" is meant to be the true trigger for RRDY & rx_holding_reg.

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          state <= 0;
      else 
        state <= resetShiftSample ? 0 : (sample_clock & (state != 8)) ? (state + 1) : state;
    end

I will run a simulation and fix this or write new one by my own.