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Altera_Forum
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14 years ago

purpuse of waitrequest

Hello I've designed a custom component which acts as an Avalon Slave. This component has a 32-bit result-register. If data are valid or not is indicated by Bit 31 (true (1) = data valid). Now I...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you for your help.

After studing the avalon specification again I have a few question more.

1) Is it correct that a "normal" read or write-access needs two cycles?

2) Can I simulate the read and write behaviour with ModelSim? Is there a master aviable?

Thank you

brunjak