Altera_Forum
Honored Contributor
8 years agoProgramming FPGA from HPS using QSPI
Hello,
I have a de1-soc I am trying to program the fpga from the qspi connected to the hps At this time I was able to load the preloader, run a bare metal application on the arm, but when I try to load the fpga me from timeout error. I edited the socfpga_common.h preloader file, defined as the CONFIG_SPL_FPGA_LOAD variable, and inserted the correct address in CONFIG_SPL_FPGA_QSPI_ADDR. The FPGA firmware is in rbf format generated by soc eds. When i start preloader i get this: U-Boot SPL 2013.01.01 (Jun 06 2017 - 13:01:59) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 925 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 370000 KHz RESET: COLD SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB FPGA : Programming FPGA SF: Read data capture delay calibrated to 3 (0 - 6) SF: Detected S25FL512S with page size 65536, total: 67108864 FPGA: Poll CD failed with error code -4# ## ERROR# ## Please RESET the board# ## Can someone help me? Thank you