Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi Andrew,
Where .sdc file is located ? For your top module it should be in the root of your project. Does it contain the constraint for system clock ? BTW I didn't see top module (verilog or vhdl) that instantiate qsys. Where is it ? Anyway, if you state, that your device isn't supported by your version of Quartus, your compilation should fail, so no .sof file generated, and consequently nothing to flash. Hope, that you'll get answer from Altera support. Regards.