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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problems downloading to NIOS II / Verification fails

Hello I am trying to interface the SD RAM on a DE0 board to a NIOS II. I have carefully followed the steps required to set up the SD RAM controller to use the IS42S16400J. Unfortunately when I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Andrew,

Where .sdc file is located ? For your top module it should be in the root of your project.

Does it contain the constraint for system clock ?

BTW I didn't see top module (verilog or vhdl) that instantiate qsys. Where is it ?

Anyway, if you state, that your device isn't supported by your version of Quartus, your compilation should fail, so no .sof file generated, and consequently nothing to flash.

Hope, that you'll get answer from Altera support.

Regards.