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Altera_Forum
Honored Contributor
Honored ContributorProblem with SDRAM
Hello Folks, i really have a problem with my Nios running on external SDRAM... I try to get my own bord running and the code has to run from SDRAM. I know the problem with the phase s...
Altera_ForumHonored Contributor
Honored ContributorYou might be better specifing a -ve clock shift.
It might be more resilient to changes in the system speed. On the cyclone III dev board I've been playing with the ssram clock is at -3.3ns. I think this value works for both 100MHz and 50MHz. That looks very similar to your +9ms at 82MHz. (The setup from altera was running at 100MHz, but I was having problems with shift instructions generating incorrect answers after I included some (possibly too slow) combinatorial custom instructions. It all worked at 50MHz with just the pll divisors changed.)
