Problem with Quartus II :(

Trech,

You could build a ring oscillator by instaniating a LCELL (Logic Cell) primitive between each inverter, but I would re-think why you are using a ring oscillator.

You can read up on the LCELL primitive by going to Quartus II help and look up "primitives". This will give you a complete list of the low level Altera primitives including the LCELL primitive component.

portion of Quartus II help:

VHDL Component Declaration:

COMPONENT LCELL

PORT (a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

VHDL LIBRARY-USE Declaration

LIBRARY altera_mf

USE altera_mf.altera_mf_components.all;

The LCELL buffer allocates a logic cell for the project. The LCELL buffer produces the true and the complement of a logic function and makes both available to all logic in the device. (The output of the LCELL buffer must feed through a NOT gate to use the complement of the logic function.)

An LCELL buffer always consumes one logic cell. It is not removed from a project during logic synthesis.

note: do not use lcell primitives to create an intentional delay or asynchronous pulse. The delay of these elements varies with temperature, power supply voltage, and device fabrication process, so race conditions can occur and create an unreliable circuit.

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You should consider a more reliable delay implementation than one that varies with temperature and process. Building ring-oscillators on a silicon chip (on any chip ASIC, FPGA etc...) in general is a risky practice with all the variations of silicon processes (i.e. you design might work today in a lab, but it could fail tomorrow in production or worse in a customer's system!). A synchronous counting device would be far more stable and reliable solution to implement.

As a final note, you would not get good device utilization if you turn off all logic optimization for the entire design. It may be possible to localize synthsis to a portion of your design, but you have to read up on all the analysis and synthsis section of Quartus II under the Assignment -> Settings jump to "Analysis and Synthsis Settings" section.

Regards,

-ATJ