Honored Contributor
Honored ContributorYes the documentation from Altera on timing isn't very easy to use. You can have a look instead at this user contributed guide:
http://www.alterawiki.com/wiki/timequest_user_guide IIRC there is a chapter on how to properly constrain an parallel interface such as your SDRAM using the setup and hold requirements from the datasheet. The derive_pll_clock command should be sufficient. You can have a look at the timequest report and see if it complains about any unconstrained clock. If it doesn't then you don't need to do anything more. Unfortunately I don't hav experience using SDRAMs so I can't help you about the pll settings and the phase shift. From what I know the phase shift to use depends on your layout and trace delays between the FPGA and the DRAM. If your SDRAM ports are still reported as unconstrained it means that Timequest didn't like the commands you put in bold. Look at the warnings from Timequest (you can search for the text "sdram_" to find them) and you should have an explanation on the reason why the command was rejected. My bet is that it didn't like the get_nets command to find the clock. You should find more information in the user guide from the Altera wiki, but as you suggested earlier the proper way to do it is to create a virtual clock and specify your input and output delays relative to that clock, if I remember correctly.
