Problem with downloading of a NIOS II program

I've advanced in my investigations ... and discovered enormous howler in the system with SDRAM: system, built in qsys lacked clock to external sdram.

I've added 2nd PLL output (please, see the qsys screenshot below)

https://www.alteraforum.com/forum/attachment.php?attachmentid=13464

The 2nd PLL output I parametrized as inspiring from an example that I've found in the board CD (though in that example SDRAM is used for different purposes)

There is phase shift on 2nd output ... and I'n not aware how its value was calculated.

Not finding an example how to build constraint file for design that interacts with external memory, I did it on my own. Here it is:

create_clock -name clk -period 20 [get_ports clk]

create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}

derive_pll_clocks

derive_clock_uncertainty

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]

set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]

set_input_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_dq*]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_dq*]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_addr*]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_bank*]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_cas_n]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_ras_n]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_cke]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_cs_n]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_we_n]

set_output_delay -clock [get_nets u0|pll|altera_pll_i|general[1].gpll~pll_output_counter|divclk] 3 [get_ports sdram_dqm*]

set_false_path -from [get_ports sw*]

set_false_path -from [get_ports key*]

set_false_path -from * -to [get_ports led*]

set_false_path -from * -to [get_ports hex*]

The essential in this constrained file is the part in bold. It manages SDRAM interface.

Here I tried to constrain input and output with respect to sdram clock that is located on [get_nets u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk] internal node.

Seemingly this .sdc file isn't correct as timing analysis produced violations, e.g. setup violations for generated clocks and ... unconstrained paths for all SDRAM ports (!!!), despite my attempt (bold part in .sdc).

but result was achieved, i.e. the "downloading issue" disappeared - in eclipse nios ii code is successfully downloaded and executed !!!

So, probably for developing further the time violation issues should I start another topic ?

Thanks.