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And I forgot to add... once you have fully constrained your design, you should check that the compiled project actually meets all the timing requirements. Timing failure will not generate an error in Quartus, but only a critical warning. If it doesn't meet your timing requirements, you can use Quartus' timing advisor to see what you can do to your project to fix the problem.
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I've revisited the case
memory: on-chip, pll: no. This time it also worked.
Concerning cases with SDRAM, I (according to your suggestion), removed false constraints on SDRAM interface.
Indeed,
timing analysis revealed violations.
Here is the content of
.sdc file I used for for the case
memory: sdram, pll: yes:
create_clock -name clk -period 20 [get_ports clk]
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_ports sw*]
set_false_path -from [get_ports key*]
# set_false_path -from [get_ports sdram_dq*]
set_false_path -from * -to [get_ports led*]
set_false_path -from * -to [get_ports hex*]
# set_false_path -from * -to [get_ports sdram*]
Here are timing analysis violations for 2 SLOW models
https://www.alteraforum.com/forum/attachment.php?attachmentid=13459 They concern clock derived from
pll. But, according to
quartus handbook, vol. 3, the command
derive_pll_clocks should resolve all
pll issues (if my comprehension is correct).
So my 1st question: should I add some constraints on the u0|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ?
Another issue from timing analysis - unconstrained path to
sdram (input and output).
The datasheet of this SDRAM chip is quite intricate ... so (2nd question) is there some straightforward approach to specify such constraints without having to consult SDRAM datasheet ... using only information on SDRAM clock frequency ?
And finally 3rd question - timing constraint on SDRAM paths should include only the following:
- set_input_delay commands for input ports (in my case only dq data bus)
- set_output_delay commands for output ports (all control signals, address bus and also dq data bus)
or should I also specify in some way the information on
sdram clock (that is 3 times external clock) ... setup virtual clock or something like this ?
Concerning external clock quality ... the external clock is generated by the "Silicon Labs" CMOS clock generator
si5350c-b. So I believe that quality should be Ok, but of course, nobody can be 100% sure.
Moreover, this external clock passes through "Clock Source" component in Qsys and then is applied to all components.
I'm not aware what this "Clock Source" is exactly ... if it's some kind of IP, probably the input signal is reshaped (???) and output clock "looks" better ?
To my opinion, the timing section is one of the most obscured in the Altera documentation.
Do exist some other sources of information on this topic ?
Thanks in advance for your comments and suggestions.
Honored Contributor
