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If my comprehension is correct, for the moment there is no any straightforward approach allowing to manage this issue.
A real disaster !!!
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Not really. Once you get a project configured correctly it will work each time. From what you are describing (changing a few things in the QSys project, and the whole CPU not working any more) it looks like you have a timing problem.
I noticed in one of your post that you defined the SDRAM interface as a false path. This will probably don't work because the SDRAM requires a very tight timing and you should fully constrain it. Check also that your clock input is constrained correctly with the correct frequency. When you are using a pll the derive_pll_clocks commands in the timequest sdc file will define for you the generated clocks. You can have a look at the clocks list in the Timequest report to check that Quartus identified all your clocks and gave them the correct frequency.
How good is your 50MHz clock source? If there are glitches it could also explain qhy the design isn't working properly when not using a pll.
Did you enter all the information in the SDRAM controller configuration, with values adapted to the SDRAM chip you are using?
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