Honored Contributor
Honored ContributorYes, you are right. The presence of pll isn't panacea for this issue.
I've created another design, a little bit more complicated - more peripherals and on-chip memory is replaced by sdram. And with this new design I've met the same problem - the nios ii code "refuse" to be downloading into board. In this new design I also used pll, but this time it didn't help (please, see the qsys screenshot below) As I understood, this issue is quite recurrent and apparently there is no any reliable workaround. http://www.alteraforum.com/forum/attachment.php?attachmentid=13368&stc=1 Concerning your remark on Timing issues, Timing analysis didn't reveal any issues. Here is the content of .sdc file: create_clock -name clk -period 20 [get_ports clk] create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] derive_clock_uncertainty set_false_path -from [get_ports sw*] set_false_path -from [get_ports key*] set_false_path -from [get_ports sdram_dq*] set_false_path -from * -to [get_ports led*] set_false_path -from * -to [get_ports hex*] set_false_path -from * -to [get_ports sdram*] This post largely repeats the previous one due to confusion, caused by website maintenance. Sorry for this misunderstanding
