Forum Discussion
Altera_Forum
Honored Contributor
8 years agoProblem resolved.
I've modified the qsys system. After adding of the pll block and applying of the pll-generated clock (143 MHz) instead of external clock 50MHz, the nios ii code is downloaded and system works correctly. Apparently the pll block plays a fundamental role in the system construction. I wonder if exists some document that treats this issue. http://www.alteraforum.com/forum/attachment.php?attachmentid=13360&stc=1 The only issue remains incomprehensible. Here is extract of the design compilation report. Warning: RST port on the PLL is not properly connected on instance nios_led:u0|nios_led_pll:pll|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. After all, as one can state from qsys screenshot, the reset signal of the pll block is connected to the clk_reset of the clk block. Thanks in advance.