Problem in getting 1 usec Interval Timer to work using NiosII and QSYS

There are a few possibilities[list][*]If you don't use a multitasking OS, a simple for loop that doesn't do anything can make a decent delay system. The Nios CPU doesn't have a lot of optimization bells and whistles, so this solution will be relatively stable. Just make a few runs with different values to calibrate your loop and find how many iterations per us you have. As long as you don't change the CPU clock frequency and have instruction cache, you'll always get the same delay.

[*]add a second timer component in your SOPC/QSYS system, defined as "full featured". This timer can be started and stopped, you can define its period, and you can read its counter value. The timer will most of the time be stopped, and when you need to wait for a certain amount of time, set the timer period to the correct number of clock cycles and start it, in the "count down once" mode. Then if the delay is short, just poll the counter value and return when you reached 0. If it is longer then you can ask the timer to throw an interrupt when the value is reached. You need to be careful when using a multitasking OS, as this solution can only be used by one task at a time.[/list]

You can find documentation about the interval timer here (http://www.altera.com/literature/ug/ug_embedded_ip.pdf) in chapter 28