Problem in getting 1 usec Interval Timer to work using NiosII and QSYS

You can get a more accurate timestamp by getting the hardware to count the ticks for you.

You could also use a tickless timer scheme to get more accurate long intervals - but they'll still be subject to interrupt latency variations and the cost of the ISR dispatch.

I'd guess that interrupt entry and exit both require a full flush of the instruction pipeline - probably 5 clocks each. You need to save and restore any registers, the register bank switching is probably also a pipelline flush.

That is 20% of the cpu time (at 100MHz) before you do anything else.

You aren't going to do anything withthat interrupt.