Problem in Generation of write_n, read_n signals in NIOS-II

Thanks Johi and Ted for your valuable time and answers. I tried both of your ways and Ted you got it correct.

In my custom core I was using TX_REGISTER, CONTROL_REGISTER, STATUS_REGISTER, SLAVE_SEL_REGISTER, ACK_REGISTER each of which was of 16-bit.

Since I was supposed to do read or write operations in these multiple registers, hence single 'read_n' or 'write_n' signal was not enough. Hence each register, I had to configure as separate Avalon_slaves. But since each of the registers were of 16-bit, hence the combination of two registers were resulting in 32-bit, hence read and write signals were getting generated but only after address gaps of 4bytes(32 bit). So I configured each of the registers as 32-bits. This solved the problem.

Any other info on this matter, please share.

Regards,

gupnaval