problem- TSEMAC SW reset bit never cleared!

The size of the memory shouldn't matter, and the fifo is more than big enough.

You really need to capture the Avalon Stream signals and compare them with what the software is trying to send to see what's going on.

i cant see the Avalon Stream signals also, it seems like they dont change i have no idea why.

i use external memory SSRAM, does it matter?

can i change the external memory to an on chip memory?

Thanks

Sharen

The memory type shouldn't matter.

Are you sure you are looking at the transmit Avalon stream? Try to trigger on the 'valid' signal

hi,

finally i could see the signal! and it is exactly what i see with the sniffer.

so where could the problem be??

i saw in the exaple of altera that they work with DDR that uses rising and falling of the clk, and the sram doesnt.. is that a problem?

( now the nios and sram are working in 50M and the tse mac, dma in 25M)

Thanks

Sharen

Could you do a copy/paste of what should be sent (what you see from the software) and what you see on the Avalon stream? (including the valid/ready/startofpacket/endofpacket signals)

It could be a DMA or cache problem.

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hi, i solve that problem, it was a clk issue. now everything seems to be ok, i dont get a respons for ping, but with a sniffer (wireshark), i can see a replay from altera, with the expected mac adress, with protocol -ip, and in the info is written "Bogus IP length (2, less the header length 24)".

i would appreciate any help or idea.

thanks

Sharen

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Could you send how you solve problem with clock?