Pointer access to component base address

The IORD macro ensures that the data cache is bypassed, which is usually what you need when you access hardware.

With the pointer access, the CPU will first check if the value is in the data cache. If it is, it will get the cached value without doing any read operation on the Avalon bus. If it isn't, it will read it the same way than IORD does (or to be more precise, it can read several addresses in a burst to fill a complete cache line).

Usually with hardware, the registers contents can change without the CPU noticing, so you don't want to cache the values.