ArthurDent
New Contributor
New ContributorPHY MDIO physical base address on Cyclone V SoC
Hi I am working on interfacing a second PHY which is connected to one of the HPS EMAC using FPGA IOs, but I have some MDIO issues on my Cyclone V SoC board. The PHY responds correctly on the MDIO in...
Hello sir,
The MDIO can be accessed via GMII_Data & GMII_Address.
Please refer to the TRM:
GMII_Address on page 18-151
The GMII Address register controls the management cycles to the external PHY through the management interface. The offset is 0x10.
GMII_Data on page 18-154
The GMII Data register stores Write data to be written to the PHY register located at the address specified in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register located at the address specified by Register 4. The offset is 0x14.
Hope this might help
Thanks
