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Altera_Forum
Honored Contributor
8 years agoHow are your timing constraints? It's possible that the timing requirements for the design are on the edge and so you might have issues with silicon to silicon variation between devices. Make sure all of your timing constraints are in place and that timing requirements are met at all four corners
On the machine that only one enumerates on, does it come up with the correct link speed? E.g. if you are targrtting gen 3, do you get gen3 or gen1. That would indicate a signalling issue in which the variation between silicon might just allow one of the boards to enumerate at a lower than targetted speed but not the other. Another option is power - one of the dev kits might be drawing a little more than the other and if the slot can't keep up it could be browning out. You could try using an external supply of not already doing so to give it a boost. Alternatively measure the 12V and 3.3V lines of the PSU with a scope to make sure they are clean and within spec.